nm stands for Nanometer. nm is a unit of measurement for length in a metrics system just like meters, centimeters,s, etc. It is used to express dimensions on the atomic scale. In technical terms, it is referred to as "process node" and "technology node". [1] You will be clear with the following metrics comparison if you cannot compare or obtain the value.

Figure 1: 5nm processor

The lithographic process of 5 nanometers (5 nm) is a semiconductor process for the production of nodes after the 7 nm process node. Its manufacturing process begins around 2020. There is no Intel processor having a 5nm process. [2] The first 5-nanometer process technology features FinFET-Transistors with nanometer with fin pitches in the 20s of nm and densest metal pitches in the 30s of nm. The 5nm processor is shown in figure 1.

• Intel is planning for developing a 5nm processor.
• TSMC and Samsung are developing a 5nm process in 2020.
• They all use EUV (Extreme Ultraviolet Lithography) lithographic process.
• TSMC, Intel, Samsung 7nm process wafer Type: Bulk
• TSMC, Intel, Samsung 7nm process wafer size: 300nm

A manufacturing process that has fewer defects per given unit area will produce more known good silicon than one that has more defects, and the goal of any foundry process is to minimize that defect rate over time. This will give the customers better throughput when making orders, and the foundry aims to balance that with the cost of improving the manufacturing process.

The measure used for defect density is the number of defects per square centimeter. Anything below 0.5/cm2 is usually a good metric, and we’ve seen TSMC pull some really interesting numbers, such as 0.09 defects per square centimetre on its N7 process node only three quarters after high volume manufacturing started, as was announced in November at the VLSI Symposium 2019. As it stands, the defect rate of a new process node is often compared to what the defect rate was for the previous node at the same time in development.

The path to 5nm is well-defined compared with 3nm. [3] After that, the landscape becomes more convoluted because foundries are adding half-node processes to the mix, such as 6nm and 4nm. Moving to any of these nodes is very expensive, and benefits are not always clear-cut.

Another point of concern is the shrinking manufacturing base. There are fewer foundries to choose from at the most advanced nodes. The foundry industry once had several leading-edge vendors, but over time the field has narrowed due to soaring costs and a dwindling customer base. Generally, fewer vendors translates into fewer technical and pricing options.

After 5nm, the next full node is 3nm. But 3nm is not for the faint of heart. The cost to design a 3nm device ranges from $500 million to $1.5 billion, according to IBS. Process development costs ranges from $4 billion to $5 billion, while a fab runs $15 billion to $20 billion, according to IBS. A 3nm finFET provides a migration path from today’s 5nm finFETs. But there are some challenges, too. In theory, the finFET hits its limit when the fin width reaches 5nm, which is close to where it is today.

Nanosheets have some advantages over finFETs. In finFETs, the gate is wrapped around on three sides of a fin. In nanosheets, the gate is on four sides of the fin, enabling more control of the current.

References:

1. https://ourtechroom.com/tech/nm-in-processor-nanometer-5nm-7nm-10nm-14nm-processor-size/
2. https://www.anandtech.com/show/16028/better-yield-on-5nm-than-7nm-tsmc-update-on-defect-rates-for-n5
3. https://semiengineering.com/5nm-vs-3nm/

Cite this article:

Vinotha D (2021), The Technology of 5nm Processor, Anatechmaz, pp. 31