Shor’s algorithm stands as a breakthrough in quantum computing due to its potential to factor large integers exponentially quicker than classical algorithms. However, implementing and evaluating this algorithm on real quantum computer hardware remains exciting due to qubit limitations, gate noise, and hardware constraints. This research presents a comprehensive performance evaluation of Shor’s algorithm using simulated quantum backends provided by Qiskit. A flexible and generic implementation is proposed, allowing dynamic input of integers to be factored, with randomized co-prime selection and automated circuit generation. The algorithm is tested on various semiprime numbers, such as 15, 21, and 35, using IBM’s Aer simulator. A major contribution of this work is the circuit-level analysis conducted both before and after transpilation. Metrics such as gate counts, circuit depth, and simulator runtime are extracted to assess scalability and resource requirements. High-resolution plots of the pre-transpiled circuits are saved to visualize algorithmic complexity, while post-transpilation metrics inform future quantum hardware feasibility. The output measurement distributions are analyzed to estimate periodicity and derive correct factors. The proposed implementation is compared with existing fixed-instance Shor demonstrations to highlight its flexibility and extensibility. Experimental results show consistent success in factor retrieval and provide valuable insight into circuit growth and complexity under realistic constraints. This analysis lays the groundwork for future adaptation to NISQ hardware and contributes to understanding Shor’s algorithm from both computational and architectural perspectives.
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CRediT Author Statement
The authors confirm contribution to the paper as follows:
Conceptualization:Thamaraimanalan T, Anandakumar Haldorai;
Methodology: Thamaraimanalan T and Anandakumar Haldorai;
Software: Mariyappan K and Arulmurugan Ramu;
Data Curation: Thamaraimanalan T and Anandakumar Haldorai;
Writing- Original Draft Preparation: Thamaraimanalan T, Anandakumar Haldorai;
Visualization: Thamaraimanalan T and Anandakumar Haldorai;
Investigation: Mariyappan K and Arulmurugan Ramu;
Supervision: Thamaraimanalan T and Anandakumar Haldorai;
Validation: Mariyappan K and Arulmurugan Ramu;
Writing- Reviewing and Editing: Thamaraimanalan T, Anandakumar Haldorai, Mariyappan K and Arulmurugan Ramu; All authors reviewed the results and approved the final version of the manuscript.
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Thamaraimanalan T
Department of Electronics and Communications Engineering, Sri Eshwar College of Engineering, Coimbatore, Tamil Nadu, India.
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Cite this article
Thamaraimanalan T, Anandakumar Haldorai, Arulmurugan Ramu and Mariyappan K, “Performance Evaluation of Shor Algorithm on Simulated Quantum Hardware with Circuit Level Analysis”, Journal of Machine and Computing, vol.5, no.3, pp. 1944-1957, July 2025, doi: 10.53759/7669/jmc202505152.
