NoC-Based Dynamic Reconfigurable Systems (DRSs) implemented over FPGA devices change their configuration at the run time by re-positioning or replacing the existing processing modules into the network. Several Dynamically Reconfigurable NoCs (DRNoCs) in the literature, propose adaptive routing algorithms in order to handle the network structure alteration. Nevertheless, their implementation cost is severe in terms of chip area and time required to reconfigure the routing scheme, which results in non-well scalable solutions for DRSs. In this work, we propose an alternative DRNoC approach, based on a traditional 2-D mesh, using a logic-based implementation of the Flexible Direction Order Routing (FDOR) algorithm, thus inheriting its simplicity and deadlock-freedom. Several scenarios have been considered in order to prove the applicability of the FDOR algorithm in the context of a DRNoC accompanied by performance and synthesis results. In conclusion, we demonstrate that FDOR is a suitable solution for DRNoCs. This project was aimed for implementing low-cost optimized FPGA architecture. Model sim 6.5f is used for simulating the NOC and synthesized using Xilinx ISE 14.7. Then the implementation is done in Spartan3 FPGA Kit.
C. Bobda and A. Ahmadinia, “Dynamic interconnection of reconfigurable modules on reconfigurable devices,” Design Test of Computers, IEEE, vol. 22, no. 5, pp. 443–451, Sept 2005.
S. Jovanovic, C. Tanougast, and S. Weber, “A new high-performance scalable dynamic interconnection for fpga-based reconfigurable systems, “in Application-Specific Systems, Architectures and Processors,2008. ASAP 2008. International Conference on, July 2008, pp. 61–66.
S. Jovanovic, C. Tanougast, C. Bobda, and S.Weber, “Cunoc: A Dynamic scalable communication structure for dynamically reconfigurable FPGAs,” Microprocessors and Microsystems, vol. 33, no. 1, pp.24 – 36, 2009, selected Papers from ReCoSoC 2007 (Reconfigurable Communication-centric Systems-on-Chip).
T. Pionteck, C. Albrecht, R. Koch, and E. Maehle, “Adaptive communication architectures for runtime reconfigurable system-on-chips,”
Parallel Processing Letters, vol. 18, no. 02, pp. 275–289, 2008.
T. Skeie, F. Sem-Jacobsen, S. Rodrigo, J. Flich, D. Bertozzi, and S. Medardoni, “Flexible dor routing for virtualization of multicore chips,” in System-on-Chip, 2009. SOC 2009. International Symposium on, Oct 2009, pp. 073–076.
J. Huang, X. Xu, N. Wang, and S. Chen, “Reconfigurable topology synthesis for application-specific NoC on partially dynamically reconfigurable systems,” Integration, vol. 65, pp. 331–343, Mar. 2019, doi: 10.1016/j.vlsi.2018.02.012.
S. Abed, “Implementation of Edge Detection Algorithm using FPGA Reconfigurable Hardware,” Journal of Engineering Research, vol. 8, no. 1, Mar. 2020, doi: 10.36909/jer.v8i1.7956.
G. P. Ramesh and S. Prabhu, “FPGA Implementation of 3D NOC Using Anti-Hebbian for Multicast Routing Algorithm,” Lecture Notes in Networks and Systems, pp. 301–313, 2021, doi: 10.1007/978-981-33-4687-1_29.
M. Rozkovec, “Implementation of Dynamically Reconfigurable Test Architecture for FPGA Circuits,” 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Apr. 2008, doi: 10.1109/ddecs.2008.4538782.
N. Kapre and A. Dehon, “An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads,” International Journal of Reconfigurable Computing, vol. 2011, pp. 1–14, 2011, doi: 10.1155/2011/745147.
Cite this article
Divyashree.K, Shwethaa.A. R, “Implementation Of Dynamically Reconfigurable NoC Using Flexible Dimension Order Routing (FDOR) Algorithm on FPGA”, Advances in Intelligent Systems and Technologies, pp. 135-137, December. 2022. doi: 10.53759/aist/978-9914-9946-1-2_25
